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Specification of the PCI Express Capabilities Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
uint8_t | intMsg |
[rw] Interrupt Message Number. Updated by hardware and writable through internal bus Interface. | |
uint8_t | sltImplN |
[rw] Slot Implemented. Writable from internal bus interface. | |
uint8_t | dportType |
[rw] Device Port Type. | |
uint8_t | pcieCap |
[rw] PCI Express Capability Version | |
uint8_t | nextCap |
[rw] Next capability pointer. Writable from internal bus interface. | |
uint8_t | capId |
[rw] PCIe Capability ID. |
Specification of the PCI Express Capabilities Register.
This register may be used for both endpoint and root complex modes.
uint8_t pciePciesCapReg_s::capId |
[rw] PCIe Capability ID.
Field size: 8 bits
uint8_t pciePciesCapReg_s::dportType |
[rw] Device Port Type.
0 = EP type
4h = RC type
Others = Reserved
Field size: 4 bits
uint8_t pciePciesCapReg_s::intMsg |
[rw] Interrupt Message Number. Updated by hardware and writable through internal bus Interface.
Field size: 5 bits
uint8_t pciePciesCapReg_s::nextCap |
[rw] Next capability pointer. Writable from internal bus interface.
Field size: 8 bits
uint8_t pciePciesCapReg_s::pcieCap |
[rw] PCI Express Capability Version
Field size: 4 bits
uint32_t pciePciesCapReg_s::raw |
[ro] Raw image of register on read; actual value on write
uint8_t pciePciesCapReg_s::sltImplN |
[rw] Slot Implemented. Writable from internal bus interface.
Field size: 1 bit