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Specification of the Gen2 Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | deemph |
[rw] Set de-emphasis level for upstream (EP) ports | |
uint8_t | txCmpl |
[rw] Configure TX compliance receive bit. | |
uint8_t | txSwing |
[rw] Configure PHY TX Swing | |
uint8_t | dirSpd |
[rw] direct speed change | |
uint16_t | lnEn |
[rw] Lane enable. 1h=x1, 2h=x2. Other values reserved. | |
uint8_t | numFts |
[rw] number of fast training sequences |
Specification of the Gen2 Register.
This register may be used for both endpoint and root complex modes.
uint8_t pcieGen2Reg_s::deemph |
[rw] Set de-emphasis level for upstream (EP) ports
Field size: 1 bit
uint8_t pcieGen2Reg_s::dirSpd |
[rw] direct speed change
0 = Indicates to the LTSSM not to initiate a speed change to Gen2 after the link is initialized at Gen1 speed.
1 = Indicates to the LTSSM to initiate a speed change to Gen2 after the link is initialized at Gen1 speed.
Field size: 1 bit
uint16_t pcieGen2Reg_s::lnEn |
[rw] Lane enable. 1h=x1, 2h=x2. Other values reserved.
Field size: 9 bits
uint8_t pcieGen2Reg_s::numFts |
[rw] number of fast training sequences
Field size: 8 bit
uint8_t pcieGen2Reg_s::txCmpl |
[rw] Configure TX compliance receive bit.
Field size: 1 bit
uint8_t pcieGen2Reg_s::txSwing |
[rw] Configure PHY TX Swing
0 = Low Swing
1 = Full Swing
Field size: 1 bit